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tm
TE CH
T14M1024A
SRAM
FEATURES
* Fast Address Access Times : 10/12/15ns * Single 5V +10% power supply * Low Power Consumption : 110/105/100mA * TTL I/O compatible * 2.0V data retention mode * Automatic power-down when deselected * Available packages : 32-pin 300 mil SOJ & 32-pin TSOP-I * Industry Standard Pin Assignment
128K X 8 HIGH SPEED CMOS STATIC RAM
GENERAL DESCRIPTION
The T14M1024A is a one-megabit density, fast static random access memory organized as 131,072
words by 8 bits. It is designed for use in high performance memory applications such as main
memory storage and high speed communication buffers. Fabricated using high performance CMOS technology, access times down to 10ns are achieved. Memory expansion by banking is easily accomplished using the chip enable pins CE1 and CE2. This device is packaged in a standard 32-pin 300 mil SOJ and 32-pin TSOP-I.
BLOCK DIAGRAM PIN CONFIGURATION
NC A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 Vcc A11 CE2 WE A12 A13 A14 A15 OE A16 CE1 I/O7 I/O6 I/O5 I/O4 I/O3
Vcc Vss A0 . . . . A16 CE1 CE2
DECODER
CORE ARRAY
DATA I/O WE OE
I/O0 . . . I/O7
SOJ
26 25 24 23 22 21 20 19 18 17
PIN DESCRIPTION
SYMBOL A0 - A16 I/O0 - I/O7 CE1,CE2 WE
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A16 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 A1 A2 A3
DESCRIPTION Address Inputs Data Inputs/Outputs Chip Select Inputs Write Enable Output Enable Power Supply Ground
A15 A14 A13 A12 WE CE2 A11 VCC NC A10 A9 A8 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
OE Vcc Vss
TSOP-I
PART NUMBER EXAMPLES
PACKAGE SPEED T14M1024A-10J SOJ 300mil 10ns T14M1024A-10P TSOP-I 8x13.4mm 10ns T14M1024A-10H TSOP-I 8x20mm 10ns
P. 1 Publication Date: SEP. 2002 Revision:E
TM Technology Inc. reserves the right to change products or specifications without notice.
tm
TE CH
T14M1024A
DC CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS
PARAMETER Power Supply Voltage Input Voltage Output Voltage Operating Temperatrue Storage Temperature Power Dissipation Short Circuit Output Current SYM Vcc VIN VOUT TOPR TSTG PD IOUT RATING -0.5 to 7.0 -0.5 to Vcc+0.5 -0.5 to Vcc+0.5 0 to +70 -55 to +150 1.0 50 UNIT V V V C C W mA
TRUTH TABLE
CE1 H
CE2 X L H H H
OE X
WE X
MODE Not Selected Not Selected Output Disable Read Write
I/O0- I/O7 High-Z High-Z High-Z Data Out Data In
Vcc
X L L L
X H L X
X H H L
I SB, I SB1 I SB, I SB1
Icc Icc Icc
OPERATING CHARACTERISTICS
(Vcc = 5V 10%, Ta = 0 to 70C)
PARAMETER Power Supply Voltage Input Low Voltage Input High Voltage Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current Standby Power Supply Current SYM. Vcc VIL VIH ILI ILO TEST CONDITIONS MIN. 4.5 -0.5 2.2 2.4 MAX. 5.5 0.8 Vcc+0.5 5 5 0.4 110 105 100 25 5 UNIT V V V uA uA V V mA mA mA mA mA
VIN =Vss to Vcc VIN=Vss to Vcc , CE1 = VIH or CE2 = VIL or OE = VIH or WE = VIL I OL = 4.0 mA I OH =-2.0 mA
CE1 =VIL
VOL VOH
Icc
10ns
I SB I SB1
12ns IO = 0mA 15ns CE1 =VIH , CE2 = VIL, IO = 0mA Vcc = max; CE1 Vcc-0.2V or CE2 Vss+0.2V; f=0mhz; IO = 0mA
CE2 = VIH ;f=max
Note: Typical characteristics are at Vcc = 5V, Ta = 25C
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 2
Publication Date: SEP. 2002 Revision:E
tm
TE CH
T14M1024A
RECOMMENDED OPERATING CONDITIONS
PARAMETER Supply Voltage Input Voltage, low Input Voltage, high Ambient Temperature SYM Vcc MIN Typ-10% -0.3 2.2 0 TYP 5 MAX Typ+10% 0.8 Vcc+0.3 70 UNIT V V V C
VIL VIH TA
CAPACITANCE
PARAMETER Input Capacitance Input/ Output Capacitance SYMBOL
C IN C I/O
CONDITION VIN = 0V VOUT = 0V
MAX. 6 8
UNIT pF pF
Note: These parameters are sampled but not 100% tested.
AC TEST CONDITIONS
PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load CONDITIONS 0V to 3V 3.0 ns 1.5V C L =30pF,I OH /I OL = -2mA/4mA
AC TEST LOADS AND WAVEFORM
5V RL=50 ohm OUTPUT Zo=50 ohm Vt=1.5V 30pF OUTPUT 5pF Including Jig and Scope R2 255 ohm R1 480 ohm
(For TCLZ, TOLZ, TCHZ, TOHZ, TWHZ, TOW )
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 3
Publication Date: SEP. 2002 Revision:E
tm
TE CH
T14M1024A
AC CHARACTERISTICS
(Vcc =5V 10%, Vss = 0V, Ta = 0 to 70C)
(1) READ CYCLE
PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable to Output Valid Chip Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z Output Hold from Address Change SYM. T14M1024A-10 T14M1024A-12 T14M1024A-15 UNIT MIN. MAX. MIN. MAX. MIN. MAX. 10 12 15 ns 3 0 3 10 10 6 5 5 3 0 3 12 12 7 6 6 3 0 3 15 15 7 7 7 ns ns ns ns ns ns ns ns
tRC tAA tACS tAOE tCLZ* tOLZ* tCHZ* tOHZ* tOH
* These parameters are sampled but not 100% tested.
(2)WRITE CYCLE
PARAMETER Write Cycle Time Chip Enable to End of Write Address Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time Data Valid to End of Write Data Hold from End of Write Write to Output in High Z Output Disable to Output in High Z Output Active from End of Write SYM. T14M1024A-10 T14M1024A-12 T14M1024A-15 UNIT MIN. MAX. MIN. MAX. MIN. MAX. 10 12 15 ns 8 8 0 8 0 6 0 0 5 5 10 10 0 10 0 8 0 0 6 6 11 11 0 11 0 8 0 0 6 7 ns ns ns ns ns ns ns ns ns ns
tWC tCW tAW tAS tWP tWR tDW tDH tWHZ* tOHZ* tOW
* These parameters are sampled but not 100% tested.
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 4
Publication Date: SEP. 2002 Revision:E
tm
(Address
TE CH
T14M1024A
TIMING WAVEFORMS READ CYCLE 1
Controlled)
tR C
A d d re s s
tA A tO H tO H
DOUT
READ CYCLE 2
(Chip Enable Controlled)
tRC
Address
tA A
OE
t AOE tOLZ tOH
CE
t ACS tCLZ tOHZ tCHZ
DOUT
DON' T CARE UNDEFINED
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 5
Publication Date: SEP. 2002 Revision:E
tm
Ad d r es s
TE CH
( OE CLOCK)
tW C
T14M1024A
WRITE CYCLE 1
t
WR
OE
tC W
CE
t AW
tW P
WE
t t AS OHZ (1,4)
DOUT
tD W tD H
DIN
WRITE CYCLE 2
( OE = V
IL
Fixed)
t WC
Ad d r es s
t CW t WR
CE
t t AW WP
WE
t AS t W HZ (1,4) t OW
t
OH
(2)
( 3)
DOUT
t DW t DH
DIN
DON'T CARE UNDEFINED
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 6
Publication Date: SEP. 2002 Revision:E
tm
TE CH
T14M1024A
Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from D OUT are the same as the data written to D IN during the write cycle. 3. D OUT provides the read data for the next address. 4. Transition is measured 500 mV from steady state with C L = 5pF. guaranteed but not 100% tested. This parameter is
5. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 7
Publication Date: SEP. 2002 Revision:E
tm
TE CH
T14M1024A
PACKAGE DIMENSIONS 32-LEAD SOJ SRAM (300 mil)
SYMBOL A A1 A2 B B1 C D E E1 e L y
DIMENSIONS IN INCHES 0.140(MAX) 0.026(MIN) 0.1000.005 0.018(TYP) 0.028(TYP) 0.008(TYP) 0.8230.005 0.3350.010 0.3000.005 0.050(TYP) 0.0860.010 0.003(MAX)
DIMENSIONS IN MM 3.556(MAX) 0.660(MIN) 2.5400.127 0.457(TYP) 0.711(TYP) 0.203(TYP) 20.9040.127 8.5090.254 7.6200.127 1.270(TYP) 2.1840.254 0.076(MAX)
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 8
Publication Date: SEP. 2002 Revision:E
tm
1
TE CH
T14M1024A
PACKAGE DIMENSIONS 32-LEAD TSOP-I (8x20mm)
HD C 32 b E e
16
17 A2 "A " A A1 Seatng pl i ane y
D
Seatng pl i ane L
D et l"A " ai
L1
SYMBOL
A A1 A2 b C HD D E e L L1
DIMENSIONS IN INCHES MIN 0.002 0.035 0.007 0.004 NOM 0.040 0.008 0.006 0.787 TYP 0.724 TYP 0.315 TYP 0.020 TYP 0.024 0.032 TYP 3 MAX 0.047 0.006 0.041 0.011 0.008
DIMENSIONS IN MM MIN 0.05 0.90 0.17 0.10 NOM 1.00 0.20 0.15 20.00 TYP 18.40 TYP 8.00 TYP 0.50 TYP 0.60 0.813 TYP 3 MAX 1.20 0.15 1.05 0.27 0.21
0.020 0
0.028 5 P. 9
0.50 0
0.70 5
TM Technology Inc. reserves the right to change products or specifications without notice.
Publication Date: SEP. 2002 Revision:E
tm
TE CH
T14M1024A
PACKAGE DIMENSIONS 32-LEAD TSOP-I (8x13.4mm)
HD C 1 32 b
E e
16
17 A2 "A " A A1 S e a t in g p la n e y
D
S e a t in g p la n e L
D e t a il " A "
L1
SYMBOL
A A1 A2 b C HD D E e L L1
DIMENSIONS IN INCHES MIN 0.002 0.035 0.007 0.004 NOM 0.040 0.008 0.006 0.528 TYP 0.465 TYP 0.315 TYP 0.020 TYP 0.024 0.032TYP 3 MAX 0.047 0.006 0.041 0.011 0.008
DIMENSIONS IN MM MIN 0.05 0.90 0.17 0.10 NOM 1.00 0.20 0.15 13.40 TYP 11.80 TYP 8.00 TYP 0.50 TYP 0.60 0.813 TYP 3 MAX 1.20 0.15 1.05 0.27 0.21
0.020 0
0.028 5
0.50 0
0.7 5
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 10
Publication Date: SEP. 2002 Revision:E

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